Area and Timing Models for PTL Macrocells
نویسندگان
چکیده
PTL represents a viable alternative to standard CMOS for the implementation of specific units in performance-constrained systems. Unfortunately, this design style has not found wide acceptance in the designers’ community, due to the lack of an established flow for automatic synthesis. In this paper, we present a procedure for constructing area and timing models for PTL macrocells. This is an key step towards the definition of a complete PTL design flow that is currently being pursued.
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تاریخ انتشار 2001